Memory Design- VLSI training in Noida

Course overview: Assessment + e-Lectures

Memory Design program is designed to help VLSI aspirants understand the basic and advance concepts required memory design engineers. It will help them identify their strength and areas of improvements to re-build their concepts. An innovative assessment technique along with personalized e-Lectures is a unique feature for VLSI Job Aspirants.

Module 2:MOS Capacitors

Module 3:Semiconductor Diode

Module 8: SRAM, Register file and ROM design introduction

Module 9:SRAM Design

a. SRAM cell structure i. Design of SRAM cell ii. Basic Read and Write operations iii. Sizing of SRAM cell iv. Layout of SRAM cell v. Voltage scaling and retention challenges b. SRAM array architecture i. Various style and trade-offs ii. How to choose suitable architecture iii. High Performance/Low Power etc. c. SRAM Periphery design i. Decoder schemes and its trade-offs ii. Design of Sense Amplifier (in detail) 1. Differential requirements and methodologies iii. Read column mux, write column mux sizing iv. Precharge transistor sizing v. Write driver vi. Input/output flop design (introduction of latch based) d. Control block and its design considerations e. Internal races and its identifications (coding of internal margins in detail) f. Leakage and Power

Module 10: Register File design

a. Register file cells i. Design of register file cells ii. Various trade-offs

Module 11: ROM Design basics

a. ROM cell design b. ROM cell layout and optimizations trade-offs

Module 12: Memory array design flow

a. Schematics b. Layouts c. LVS/DRC d. RTL views and its need e. Functional verification and its need i. Introduction to different available tools f. Characterization details i. Setup/Hold/Access time/Cycle time ii. Leakage iii. Power iv. Energy v. Liberty formats and its representations g. Handoff’s for different deliverables h. Verification of different deliverables i. Quality checks

Module 13: Design for variations

Module 14: Advance memory architecture

a. High performance b. Ultra-low power architecture

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Memory Design

Duration

12 Weeks

Categories

VLSI

1 year validity of Assessment Tool

Course overview: Assessment + e-Lectures

Certification

Training Delivery Model

Who can attend

Curriculum

Module 1: Introduction to Resistors and Capacitors

Module 2:MOS Capacitors

Module 3:Semiconductor Diode

Module 4 :MOS Transistor at device level

Module 5: Introduction to Technology node and trends of memory design

Module 6: . Memory Hierarchy

Module 7: Types of Memories

Module 8: SRAM, Register file and ROM design introduction

Module 9:SRAM Design

Module 10: Register File design

Module 11: ROM Design basics

Module 12: Memory array design flow

Module 13: Design for variations

Module 14: Advance memory architecture

Module 15: Future and recent trends for memory design

Related Courses

VLSI Assessment Papers

Physical Design

Layout Design

Standard Cell Design

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