1) Overview of Verilog & Hierarchical modeling concept
2) Module and port & Basic concept
3) Gate Level modeling
4) Data flow modeling
5) Behavioral modeling
6) Task and Function
7) Timing and Delays
8) UDP
9) Logic Synthesis
10) Useful modeling Techniques

Project:
1) Designing of one small project using Verilog
2) Designing of one Protocol using Verilog

1) Overview of System Verilog & Verification process
2) Data types
3) Task and Function, Queue, Fixed array, Dynamic array, Associative array
4) Package, Interface, Program block, Clocking block
5) OOP
6) Inter Process Communication (Mailox, Semaphore, Event)
7) Randomization
8) Coverage
9) Assertion
10) Verification Environment

Project:
1) Verification Environment for Small project using system Verilog
2) Verification Environment for Protocol using system Verilog

1) Overview of UVM & verification process
2) UVM Testbench
3) UVM Class Library
4) UVM Object and Component
5) UVM Factory
6) UVM Reporting
7) UVM Configure
8) UVM Phase
9) UVM TLM 1.0
10) UVM Callback

Project:
1)Verification Environment for Small project using UVM
2) Verification Environment for Protocol using UVM

1) Basic cmd: pwd, ls, touch, mv, cp rm, mkdir, cat, etc.
2) Filters : grep, cut, tac, tr, find, comm, diff, uniq, sed, awk etc.
3) Editor : vi and gedit
4) Shell scripting

1) Constant Variable and Data Type
2) Operators and Expression
3) Decision Making and Looping
4) Function
5) Array
6) String
7) Pointers
8) Structures and Unions
9) Dynamic Memory Allocations

1) Beginning with C++
2) Tokens Expressions and Control Structure
3) Functions in C++
4) Classes and Objects
5) Constructors and Destructors
6) Operator Overloading and Type Conversions
7) Introduction to the Standard Template Library
8) Extending Classes
9) Pointers Virtual Functions and Polymorphism